FPGA · Visual Servo · Motor Control

Advanced Visual Servo
Systems for the World

RealTime eLab develops cutting-edge FPGA IP cores for PMSM servo drives and visual motion controllers — precision engineering for the next generation of industrial automation.

Explore IP Cores Tech Column
4+
IP Core Modules
2019
Founded
Xilinx
FPGA Platform
01
EnDat 2.1/2.2
High-precision encoder interface IP with APB32 bus integration
02
FOC / SVPWM
Field Oriented Control and Space Vector PWM for PMSM drives
03
PID Controller
Digital PID implementation optimized for real-time servo loops
04
Digital Filters
LPF · HPF · BPF · BSF and more, all synthesizable on FPGA
Our Mission

Bridging Vision and Motion

Founded in 2019 by Dr. Qielu Pan, RealTime eLab focuses on the intersection of computer vision and servo control — a field pioneered through the NVMM-based visual servo theory developed in 2000. Our IP cores are battle-tested and available for licensing.

Learn about Dr. Pan →
Founder & Principal Engineer

About RealTime eLab

A research-driven engineering lab focused on FPGA-based servo systems, visual motion control, and advanced motor drives.

Dr. Qielu Pan
Available IP Cores
01
EnDat 2.1/2.2 Interface
02
PID Controller
03
FOC & SVPWM
04
Digital Signal Filters

In March 2019, Dr. Qielu Pan founded RealTime eLab with the aim of developing advanced visual servo systems — an area he has been pioneering since 2000, when he first proposed the NVMM-based (Normalized Visual Motion Model) visual servo theory.

The lab's current focus is on FPGA IP core development using Xilinx platforms, targeting PMSM servo drives and visual motion controllers for industrial automation and robotics applications. All IP cores are available for licensing to manufacturers in the field.

2000
Proposed NVMM-based visual servo theory — a foundational contribution to the field of visual servoing
2019
Founded RealTime eLab; began development of FPGA-based servo and vision IP cores
2020
Published FPGA-based Digital Filter Design Methodology — LPF/HPF/BPF/BSF implementations
2021
Released FOC and SVPWM modules on FPGA; full Field Oriented Control for PMSMs
2022
Completed EnDat 2.1/2.2 master IP with APB32-bus interface — independently designed
Dr. Pan's LinkedIn Profile →
FPGA IP Cores

Product Catalog

All IP cores are developed for Xilinx FPGA platforms. Contact us for licensing, integration support, or custom development inquiries.

Encoder Interface
EnDat 2.1 / 2.2
High-precision encoder interface IP core with full APB32 bus integration. Supports both EnDat 2.1 and 2.2 protocol variants.
Xilinx FPGA APB32 Bus Serial Protocol
View Datasheet
Motor Control
FOC & SVPWM
Field Oriented Control and Space Vector PWM module for PMSM drives. High-performance, low-latency implementation on FPGA fabric.
PMSM Drive FOC Real-time
View Datasheet
Control Loop
PID Controller
Digital PID controller IP core optimized for precision servo loops. Configurable gains, anti-windup, and derivative filtering included.
Servo Loop Anti-windup Configurable
View Datasheet
Signal Processing
Digital Filters
Comprehensive library of FPGA-synthesizable digital filters: LPF, HPF, BPF, BSF. Fixed-point and floating-point variants available.
LPF / HPF BPF / BSF DSP
View Datasheet
Coming Soon
Visual Servo Controller
NVMM-based visual motion controller IP core. In active development — contact us for early access or collaboration.
NVMM Vision In Development
LICENSING & CUSTOMIZATION
All IP cores are available for licensing. Custom development and integration support on request.
Contact for Licensing
Technical Publications

Tech Column

In-depth technical articles on FPGA design methodology, motor control theory, and visual servo systems authored by Dr. Qielu Pan.

Apr 22, 2022
How To Design an EnDat 2.1/2.2 Interface Module on FPGA
Independently designed EnDat master IP with APB32-bus interface. Full protocol implementation walkthrough.
→
Aug 18, 2021
Field Oriented Control (FOC) for PMSMs
Complete design and implementation of FOC and SVPWM modules on Xilinx FPGA for permanent magnet synchronous motor control.
→
Dec 14, 2020
FPGA-based Digital Filter Design Methodology
Systematic approach to implementing LPF, HPF, BPF, and BSF filters in FPGA fabric with fixed-point arithmetic.
→
Dec 10, 2019
Visual Servoing Based on the NVMM Model
Introduction to the Normalized Visual Motion Model (NVMM) proposed by Dr. Pan in 2000 — a novel theoretical framework for image-based visual servo control.
→
Topic Areas
FPGA Design Motor Control Visual Servo Signal Processing Encoder Interfaces PID Control PMSM Drives Digital Filters
Get In Touch

Contact Us

Interested in licensing an IP core, technical collaboration, or have a custom development inquiry? Reach out directly.

Telephone
(+1) 442-444-0008
LinkedIn
Dr. Qielu Pan
Address
555 Dong Chuan Rd., Shanghai, China 200240
SEND AN INQUIRY
Send via Email
Or email directly: panqielu@visualservo.com